Asynchronous Primitives in CML - ppt download
Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
4-bit Counter Using High-Speed Low-Voltage CML D-Flipflops | Semantic Scholar
Current Mode Logic Divider
Performance evaluation of the low-voltage CML D-latch topology - ScienceDirect
Electronics | Free Full-Text | 40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors
Figure 1 from High speed CML latch using active inductor in 0.18μm CMOS technology | Semantic Scholar
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
High Speed Digital Blocks
Analysis and Design of High-Speed CMOS Frequency Dividers
A Dynamic Current Mode D-Flipflop for High Speed Application | Semantic Scholar
Electronics | Free Full-Text | High-Speed Wide-Range True-Single-Phase-Clock CMOS Dual Modulus Prescaler
Circuit configuration of the CML-type SR-latch circuit a Circuit... | Download Scientific Diagram
Circuit configuration of the CML-type SR-latch circuit a Circuit... | Download Scientific Diagram
DFF-based CMOS clock divider. | Download Scientific Diagram
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
Electronics | Free Full-Text | A High-Speed Low-Power Divide-by-3/4 Prescaler using E-TSPC Logic DFFs
Circuit configuration of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
A Novel Ultra High-Speed Flip-Flop-Based Frequency Divider
Low Power Rail to Rail D Flip-Flop Using Current Mode Logic Structure
An active inductor employed CML latch for high speed integrated circuits | SpringerLink
High Speed Digital Blocks
OAK 국가리포지터리 - OA 학술지 - Transactions on Electrical and Electronic Materials - High-speed CMOS Frequency Divider with Inductive Peaking Technique
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
A Dynamic Current Mode D-Flipflop for High Speed Application
Figure 2 from New CML latch structure for high speed prescaler design | Semantic Scholar
